The present invention is related to an analog switch, and a sample-and-hold circuit for an analog input voltage. More specifically, the present invention is directed to such a technique capable of reducing an adverse influence caused by such a voltage which has already been inputted into an analog multiplexer. For instance, the present invention is pertinent to such an effective technique which is utilized in an A/D converting circuit, and also a single-chip microprocessor computer having the A/D converting circuit therein.
In an A/D (analog-to-digital) converting circuit, and a semiconductor integrated circuit containing this A/D converting circuit, an analog switch, and a sample-and-hold circuit are employed. The analog switch is used so as to conduct an analog input voltage from an external source, and this analog input voltage should be A/D-converted. The sample-and-hold circuit holds the analog input voltage while being A/D-converted. Also, in the case that there are plural analog signals derived from a plurality of sensors as realized in a control system for an automobile, when each of these plural analog signals is A/D-converted into a digital signal by using a respective one of the individual A/D converting circuits, a total number of these A/D converting circuits becomes large, so that cost of the automobile control system would be increased. As a consequence, such an automobile control system may be sometimes arranged in such a manner that a plurality of analog input voltages are A/D-converted in a time divisional manner by employing a single A/D converting circuit.
FIG. 20 represents such a time-divisional type A/D converting system. This system is arranged as follows: That is, in this A/D converting system, a plurality of analog input voltages Vin1, Vin2, - - - , Vinn are selected by a multiplexer MPX one by one, and then, the selected analog input voltages are acquired by a sample-and-hold circuit SH. Thus, a plurality of analog input voltages are A/D-converted in the time divisional manner by using a single A/D converting circuit ADC.
In the A/D converting system as indicated in FIG. 20, analog switches SWc1 to SWcn which constitute the multiplexer MPX, and a sampling switch SWs of the sample-and-hold circuit SH are constituted by employing MOSFETs. On the other hand, in the A/D converting system of FIG. 20, a stray capacitance Ca is produced at a connection node N0 between the analog switches SWc1 to SWcn of the respective channels which constitute the multiplexer MPX, and the sampling switch SWs which constitutes the sample-and-hold circuit SH.
The production of the above-described stray capacitance Ca is caused by a junction capacitance and a wiring capacitance between a source (drain) and a main body (well) of an MOSFET. When the Inventors of the present invention tried to calculate such a stray capacitance of a circuit having 8 channels, this stray capacitance was approximately 30 pF (picofarad). Also, another stray capacitance Ca is produced at an input terminal of an A/D converting circuit 30 of FIG. 20. Furthermore, as a capacitance value of a sampling capacitor Cs which constitutes this sample-and-hold circuit SH, such sampling capacitors having capacitance values of, for example, approximately 5 to 6 pF are used.
On the other hand, in order to improve the response characteristic of the sample-and-hold circuit SH, impedances (ON-resistances) of the analog switches SWc1 to SWcn, and also an impedance (ON-resistance) of the sampling switch SWs are preferably made low. For instance, in the case that sampling time is selected to be on the order of 3 xcexcs (microseconds), an impedance of such a sample-and-hold circuit may be preferably selected to be lower than, or equal to 1 kxcexa9 (killoohms).
However, the following risk problem can be revealed. That is, when the channels are switched by the multiplexer MPX, if the impedances of the analog switches SWc1 to SWcn are low and further the stray capacitance Ca is produced at the connection node N0 between the analog switches SWc1 to SWcn and the sampling switch SWs, the electron charge which has been stored in this stray capacitance Ca before the channels are switched may give an adverse influence to a level of a next analog input voltage which is inputted via such an analog switch which is turned ON after the channels are switched by the multiplexer MPX. As a result, an error of the analog input voltage to be sampled would be increased.
To avoid this problem, in such a control system as shown in FIG. 20 in which while the channels are switched by the multiplexer MPX, the A/D converting operation is carried out in the time divisional manner, it is preferable to connect externally-connectable capacitors Ci1 to Cin each having capacitances of approximately 0.1 xcexcF to the respective analog input terminals AIN1 to AINn. The reason why the error can be reduced is given as follows. That is, when such externally-connectable capacitances Ci1 to Cin are connected to these analog input terminals AIN1 to AINn, electron charges are redistributed via such an analog switch which is turned ON between the stray capacitance Ca and any one of these externally-connectable capacitors Ci1 to Cin, which may reduce the error of the analog input voltage to be sampled.
FIG. 21 graphically shows a relationship between an internal impedance Rin of an analog signal source and an error xcex4 (LSB) of an analog input voltage Vin to be sampled, assuming now that the capacitance values of the externally-connectable capacitors Ci1 to Cin which are connected to the analog input terminals AIN1 to AINn are constant. In this case, it is so assumed that the error xcex4 (LSB) may be expressed by the following formula (1) under such a condition that resolution of the A/D converting circuit is selected to be 10 bits, a reference voltage is selected to be Vref, and also a voltage which is actually acquired into the sampling capacitor Cs is selected to be xe2x80x9cVsxe2x80x9d:
xcex4(LSB)=(Vinxe2x88x92Vs)/(Vref/1024)xe2x80x83xe2x80x83(1)
In this drawing of FIG. 21, a solid line xe2x80x9caxe2x80x9d indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.1 xcexcF. A broken line xe2x80x9cbxe2x80x9d indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.07 xcexcF. Also, a dotted line xe2x80x9ccxe2x80x9d indicates such an error plotted in the case that the capacitance value of the externally-connectable capacitor Ci is equal to 0.05 xcexcF.
It should be noted that the relationship of FIG. 21 is obtained under the below-mentioned condition: That is, a range of an operation voltage is selected to be zero V to +0.5 V and xe2x88x920.5 V; sampling time of an analog input voltage is selected to be 3.2 xcexcS; an equivalent capacitance value (Ca+Cs+Cd) defined from an analog input terminal AIN up to a sample-and-hold circuit is selected to be approximately 50 pF; and further, both an equivalent impedance of an analog switch SWc of a multiplexer and another equivalent impedance of a sampling switch SWs own such a characteristic represented in FIG. 22. In FIG. 22, a curve indicated as a symbol xe2x80x9cWORSTxe2x80x9d denotes an impedance of such an element having the largest fluctuation. Also, a curve indicated as a symbol xe2x80x9cTYPxe2x80x9d denotes an impedance of a typical element.
The following fact can be seen from FIG. 21. That is, the larger the capacitance values of the externally-connectable capacitors Ci1 to Cin of the analog input terminals AIN1 to AINn become, the smaller the error is decreased. However, when the capacitance values of the externally-connectable capacitors Ci1 to Cin are increased in an automobile control system, the following fact could be revealed. That is, there is a certain possibility that precision of the A/D converting operation is lowered. Under such a circumstance, the Inventors of the present invention has considered this reason of lowering of the A/D converting precision. As a result, the following fact can be revealed:
In such a system which is operated under the worst environment where external noise is increased similar to a control system of an automobile, since an S/N (signal-to-noise) ratio of a sensor functioning as an analog signal source is improved, a series resistor (resistance values of several tens to several hundreds Kxcexa9) may be arranged between an analog input terminal of an A/D converter and a signal of the sensor so as to constitute a filter circuit. Alternatively, such a sensor circuit having several tens to several hundreds Kxcexa9 as an overall impedance of an analog signal source may be employed. As a consequence, the Inventors of the present invention could predict that a response characteristic of an input voltage in this control system may cause the above-explained reason, and firstly, have considered the response characteristic of this control system with respect to the input voltage. Concretely speaking, while the Inventors of the present invention considered that a voltage VA(i) which is entered into an analog input terminal AIN(i) is changed in an exponential manner as represented in FIG. 23, such a formula capable of expressing a temporal change of this inputted analog voltage was obtained. This formula is given as follows:
VA(i)=Vin(Txe2x88x921)+xcex94V (1xe2x88x92e (xe2x88x92t/(Cixc2x7Rin)))xe2x80x83xe2x80x83(2)
In this formula(2), symbol xe2x80x9cVin(Txe2x88x921)xe2x80x9d shows a voltage appeared before the analog input voltage VA(i) is changed.
Next, under such a condition that the error xcexa9(LSB) of the analog input voltage Vin is equal to 0.1, the reference voltage Vref of the A/D converting circuit is equal to 5.0 V, and also the capacitance value of the externally-connectable capacitor Ci is equal to 0.1 xcexcF, such a delay time was calculated while the internal impedance value Rin of the signal source was changed and also the magnitude of the changed voltage xe2x80x9cxcex94Vxe2x80x9d was changed. This delay time is defined by that the input voltage Vin is reached to 0.1 (LSB) lower than a final voltage, namely is reached up to 0.5 mV. The calculation result of this delay time is graphically represented in FIG. 24. As apparent from FIG. 24, the following fact can be revealed. That is, the larger the internal impedance Rin of the signal source is increased and also the higher the changed voltage xe2x80x9cxcex94Vxe2x80x9d becomes, the longer the delay time is increased.
Also, as apparent from the above-explained formula(1), since a change in the input voltages Vin will depend upon such a time constant (CR) defined between the internal impedance Rin and the externally-connected capacitor Ci of the analog input terminal, the larger the capacitance value of this externally-connectable capacitor Ci is increased, the longer the delay time is prolonged (similar to the internal impedance Rin). For example, in FIG. 24, a broken line xe2x80x9cCxe2x80x9d which represents a delay time-to-changed voltage characteristic in the case that the internal impedance Rin is equal to 5 kxcexa9 may become equal to another broken line xe2x80x9cBxe2x80x9d which indicates a delay time-to-changed voltage characteristic in such a case that the internal impedance Rin is equal to 10 kxcexa9 when the capacitance value of the externally-connectable capacitor Ci becomes 0.2 xcexcF. This first-mentioned broken line xe2x80x9cCxe2x80x9d may become equal to a further broken line xe2x80x9cAxe2x80x9d which represents a delay time-to-changed voltage characteristic in the case that the internal impedance Rin is equal to 20 kxcexa9 when the capacitance value of the externally-connectable capacitor Ci becomes 0.4 xcexcF.
On the other hand, even in a control system used under such an environment that a large number of external noise is present (similar in an automobile control system), it is practically difficult that internal impedances of all of sensors functioning as an analog signal source are reduced. In other words, in such an automobile control system, such a sensor whose internal impedance is high must be necessarily employed. Also, because of a distance relationship between a setting position of a sensor and a setting position of an A/D converter, a series resistor functioning as an external-noise-problem solution is provided in front of an analog input terminal, so that an impedance of a signal source is increased. However, as explained above, if the capacitance value of the externally-connectable capacitor Ci is increased, then delay time is prolonged. As a result, this capacitance value of the externally-connectable capacitor Ci cannot be excessively increased. As a consequence, in such a control system, the capacitance value of the externally-connectable capacitor Ci must be made small in the case that a sampling period should be prolonged so as to secure A/D converting precision, or conversely in such a case that the sampling period is shortened so as to secure a favorable response characteristic to some extent. Accordingly, there is such a problem that the A/D converting precision would be sacrificed.
An object of the present invention is therefore to provide both an analog switch and an analog multiplexer, by which an electron charge which has been stored in a stray capacitance before a switch is switched does not give an adverse influence to a level of a subsequent analog input voltage which is entered thereinto after the switch is switched.
Another object of the present invention is to provide such an A/D converting circuit capable of A/D-converting an analog input voltage in high precision.
A further object of the present invention is to provide such an A/D converting circuit capable of performing a high-precision A/D converting operation, while a high response speed thereof can be realized.
A still further object of the present invention is to provide such an A/D converting circuit capable of performing a high-precision A/D converting operation without lowering an S/N ratio thereof.
Typical inventive ideas selected from inventive ideas disclosed in the present invention will be briefly described as follows:
An analog switch circuit is constituted by a transfer gate made up of insulating gate type transistors, and a voltage follower connected in parallel to the transistors, and the analog switch circuit is arranged in such a manner that after the voltage follower is brought into an active state, the transistors are conducted.
In accordance with the above-explained means, it is possible to avoid such a condition that an adverse influence caused by a potential appeared on the output side is transferred via the analog switch brought into the ON state to the output side. In other words, electric charges which have been stored in a stray capacitance provided on the output side thereof before a switch is switched do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched.
Also, preferably, the above-described transfer gate is made as a CMOS transfer gate constituted by both a p-channel MOSFET and an n-channel MOSFET, which are connected in parallel to each other between an analog input terminal and an analog output terminal. Since the CMOS transfer gate is employed, not only a signal having a high potential, but also a signal having a low potential can be transferred without lowering a signal level.
Furthermore, the above-described insulating gate type transistor is preferably constituted by two transistors, the channels of which are connected in a series connection mode. Also, these two transistors are formed on different well regions which are formed on a semiconductor substrate. Since the analog switch circuit is constituted by the two transistors connected in the series connection mode, it is possible to avoid such an operation that a change in analog input signals is transferred to the output terminal side via a stray capacitance produced between sources and drains of these transistors. Also, since the two transistors connected in the series connection mode are formed on the different well regions, the following operation can be prevented. That is, a current is captured from the output terminal side by minority carriers which are produced in well regions in such a case that a negative voltage is applied to the input terminal, so that the potential is changed, which can be avoided by this analog switch circuit.
A multiplexer circuit, according to the present invention, is such that a plurality of analog switch circuits are constituted by a plurality of transfer gates each made up of an insulating gate type transistor, and voltage followers connected in parallel to channels of these transistors; and one terminal of these analog switch circuits are connected to a plurality of analog input terminals, whereas other terminals of these analog switch circuits are connected to a common output terminal. When any one of these analog switch circuits is selectively turned ON, the voltage follower of this relevant switch circuit is first brought into an active state, and thereafter, the insulating type transistor is set to the conductive state.
In accordance with the above-described means, it is possible to avoid such a phenomenon that an adverse influence caused by a potential appeared on the output side via the analog switch which is brought into the ON state is transferred to the side of the input terminal. Also, electric charges which have been stored in a stray capacitance provided on the output side thereof before the multiplexer circuit is switched do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the multiplexer circuit has been switched.
Also in this multiplexer circuit, the above-explained transfer gate may be preferably made as a CMOS transfer gate constituted by both a p-channel MOSFET and an n-channel MOSFET, which are connected in parallel to each other between the analog input terminal and the analog output terminal. Furthermore, the above-described insulating gate type transistor is preferably constituted by two transistors, the channels of which are connected in a series connection mode. Also, these two transistors are formed on different well regions which are formed on a semiconductor substrate.
Also, an A/D converting circuit, according to the present invention, is featured by employing a sample-and-hold circuit which is constituted by an analog switch circuit and a sample-and-hold circuit made up of a sampling capacitor. This analog switch circuit is arranged by an insulating gate type transistor, and a voltage follower which is connected in parallel to a channel of this insulating gate type transistor. The above-explained sampling capacitor is connected to an output terminal of the voltage follower circuit.
In accordance with the above-described means, it is possible to avoid such a phenomenon that an adverse influence caused by a potential appeared on the output side via the analog switch circuit which is brought into the ON state is transferred to the side of the input terminal. Also, the analog input signal can be sampled in high precision. As a result, the high-precision A/D converting operation can be carried out. Further, even when a capacitance value of an externally-connectable capacitor is decreased which is connected to the analog input terminal, the higher A/D converting precision can be achieved. Therefore, even when such an analog signal source having a high internal impedance is employed, namely even when such an analog signal source capable of withstanding noise aspects is used, propagation delay time of an input signal can be shortened. As a consequence, in such a system in which a plurality of analog signals are A/D-converted by a single A/D converting circuit in the time divisional manner, while using the multiplexer, the sampling period can be shortened without sacrificing the A/D conversion precision, and also, the A/D converting operation with the better response characteristic can be carried out.